QT300(2003) データシートの表示（PDF） - Quantum Research Group
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QT300 Datasheet PDF : 12 Pages
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Figure 3-1 Multiple QT300's on the same SPI port
A typical SPI slave mode communication sequence is:
DRDY
Host Micro SCK
SDI
Vdd
100nF
QT 300 8
Vcc
1
DRDY
2
3
SCK SNS 1
6
5
REQ SNS 2
CS
7
SDO
GND
4
SENSOR
Vdd
100nF
QT 300 8
Vcc
1 DRDY
2
3
SCK SNS 1
6
5
REQ SNS 2
CS
7
SDO
GND
4
SENSOR
Vdd
100nF
QT 300 8
Vcc
1
DRDY
2
3
SCK SNS 1
6
5
REQ SNS 2
CS
7
SDO
GND
4
SENSOR
1) Host pulses /REQ low for ≥30µs to initiate an acquire.
2) QT300 acquires a signal in response to /REQ.
3) QT300 pulls /DRDY low when ready to send data back.
4) Host detects /DRDY is low.
5) Host clocks out the high byte of data from the QT300.
6) Host waits for ≥12µs.
7) Host clocks out the low byte of data from the QT300.
8) QT300 releases /DRDY to float high.
3.5 SPI Master Mode
Refer to Figure 7-2 and Table 7-2, page 8.
In master SPI mode the QT300 generates the clock signal
after an acquire initiated from the host via the /REQ line. The
clock speed and the spacing between the two bytes is set via
the Setup process (Section 6).
SCD setup parameter determines the master-mode clock
rate. The default value is 55 (resulting in a 2.55KHz rate).
The relationship is:
Fscd = 1200/(30+ (SCD x 8)) in Khz
Where SCD = 0..255
SDO - Serial Data Output; Output-only. This is the data
output to the host during an SPI transfer. When not in use,
this pin floats. This pin should be connected to the SDI
input pin of the host device.
SCK - SPI clock; Idle high or idle low; input-only SPI clock
from the host. The idle state is determined in Setups by
the serial mode (SM) parameter.
If SM is set for idle-low SCK: Data is shifted out of the
QT300 on the rising edge of SCK and should be shifted
into the host on the falling edge of SCK.
If SM is set for idle-high SCK: Data is shifted out of the
QT300 on the falling edge of SCK and should be shifted
into the host on the rising edge of SCK.
The maximum clock speed is 40kHz, and the timings
should obey the parameters Tskh and Tskl in Table 7-1.
/DRDY - Data Ready; active low output only. This indicates to
the host that the device is ready to send data back to the
host. During idle times this pin floats and therefore must
be connected to a pullup resistor. The host must wait until
/DRDY goes low before starting an SPI transfer.
Between the high and low byte clockings, the host should
observe a delay of ≥12µs.
MLS setup parameter determines the spacing between the
two return bytes; this can be important to allow a slow host
device to recover from receiving the first byte to prevent an
overrun. The default value is 148 (resulting in a 500µs gap).
The relationship is:
Tmls (in µs) = (10 + MLS x 4) / 1.2
Where MLS = 0..255 (from user setup MLS)
Master SPI mode requires at least 3 signals to operate:
/REQ - Request Acquisition Input; Active low input-only.
When /REQ is pulled low, the QT300 wakes and starts an
acquire. The IC will transmit the resulting data only when
the acquire has finished.
/REQ must return high before the end of the burst. If
/REQ is still low at the end of the burst the part goes into
Setup mode. The minimum duration of /REQ is 30µs.
SDO - Serial Data Output; Idle low output-only. This is the
data output to the host during an SPI transfer. When not in
use, this pin floats. This pin should be connected to the
SDI input pin of the host device.
SCK - SPI clock; Idle high or idle low, output-only. The idle
state is determined in Setups by the serial mode (SM)
parameter.
If SM is set for idle-low SCK: Data is shifted out of the
QT300 on the rising edge of SCK and should be shifted
into the host on the falling edge of SCK.
If SM is set for idle-high SCK: Data is shifted out of the
QT300 on the falling edge of SCK and should be shifted
into the host on the rising edge of SCK.
The maximum clock speed is 40kHz, and the timings
should obey the parameters Tskh and Tskl in Table 7-2.
/DRDY - Data Ready (Optional); active low output only. This
indicates to the host that the device is ready to send data
LQ
4
QT300 R1.01 21/09/03
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