PM7367 データシートの表示（PDF） - PMC-Sierra

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PM7367

FRAME ENGINE AND DATALINK MANAGER

PMC-Sierra 

DATA SHEET

PMC-1991499

ISSUE 2

PM7367 FREEDM-32P32

FRAME ENGINE AND DATA LINK MANAGER

· Supports two levels of non-preemptive packet priority on each transmit

channel. Low priority packets will not begin transmission until all high priority

packets are transmitted.

· Alternatively, for each channel, the transmitter supports a transparent mode

where each octet is inserted transparently from host memory. For

channelised links, the octets are aligned with the transmit time-slots.

· Directly supports a 32-bit, 33 MHz PCI 2.1 interface for configuration,

monitoring and transfer of packet data, with an on-chip DMA controller with

scatter/gather capabilities.

· Provides 8 kbytes of on-chip memory for partial packet buffering in each

direction. This memory can be configured to support a variety of different

channel configurations from a single channel with 8 kbytes of buffering to 32

channels, each with a minimum of 48 bytes of buffering.

· Supports PCI burst sizes of up to 128 bytes for transfers of packet data.

· Pin compatible with PM7366-PI (FREEDM-8 PBGA) device.

· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board

test purposes.

· Supports 3.3 and 5 Volt PCI signaling environments.

· Low power CMOS technology.

· 272 pin Plastic ball grid array (PBGA) package (27 mm X 27 mm).

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 2

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