PM4332 データシートの表示（PDF） - PMC-Sierra

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PM4332

HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER

PMC-Sierra 

PRELIMINARY

DATA SHEET

PMC-2011402

ISSUE 1

PM4332 TE-32

HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER

• H-MVIP access for Channel Associated Signaling is available with the

Scaleable Bandwidth Interconnect bus as an optional replacement for CAS

access over the SBI bus as well as with the H-MVIP data interface. Common

Channel Signaling H-MVIP access is available with the SBI bus, serial PCM

and H-MVIP data interfaces.

• Alarm status, T1 F-bit and inband signaling control is available using

otherwise unused bit positions.

• Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s.

Scaleable Bandwidth Interconnect (SBI) Bus:

• Provides a high density byte serial interconnect for all TE-32 links. Utilizes an

Add/Drop configuration to asynchronously multiplex up to 32 T1s or 32 E1s

with multiple payload or link layer processors.

• External devices can access framed T1s and framed E1s over this interface.

• Framed T1 access can be selected on a per T1 basis. Framed E1 access

can be selected on a per E1 basis.

• At the system interface, synchronous access for T1 DS0 channels or E1

timeslots is supported in a locked format mode. Selectable on a per tributary

basis.

• At the system interface, channel associated signaling bits for channelized T1

and E1 are explicitly identified across the bus.

• Transmit timing is mastered either by the TE-32 or a layer 2 device

connecting to the system interface SBI bus. Timing mastership is selectable

on a per tributary basis, where a tributary is either an individual T1, E1.

• The line side SBI bus provides a time switch capability in support of

redundancy.

• The system side SBI operates at either 19.44 MHz or 77.76 MHz. The line

side SBI operates at 19.44 MHz.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS

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