PRELIMINARY
DATA SHEET
PMC-2011402
ISSUE 1
PM4332 TE-32
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
• Provides minimum ones density through Bell (bit 7), GTE or “jammed bit 8”
zero code suppression on a per-DS0 basis. Provides a 128 byte buffer to
allow insertion of the facility data link using the host interface.
• Supports transmission of the alarm indication signal (AIS) or the Yellow alarm
signal in SF, SLC96 and ESF formats.
• Provides transparency for the F-bit to support SLC96 data link insertion.
• Autonomously transmits an ESF Performance Report Message each second.
• Provides a digital phase locked loop for generation of a low jitter transmit
clock.
• Provides a FIFO buffer for jitter attenuation and rate conversion in the
transmitter.
• Supports the alternate ESF CRC-6 calculation for Japanese applications.
• A pseudo-random sequence user selectable from 27 –1, 211 –1, 215 –1 or 220 –
1, may be inserted into the T1 stream in either the ingress or egress
directions. The pseudo-random sequence can be inserted into the entire T1 or
any combination of DS0s within the framed T1.
Each one of 32 E1 transmitter sections:
• Provides a FIFO buffer for jitter attenuation and rate conversion in the
transmit path.
• Transmits G.704 basic and CRC-4 multiframe formatted E1.
• Supports unframed mode and framing bit, CRC, or data link by-pass.
• Provides signaling insertion, programmable idle code substitution, digital
milliwatt code substitution, and data inversion on a per channel basis.
• Provides trunk conditioning which forces programmable trouble code
substitution and signaling conditioning on all channels or on selected
channels.
• Provides a digital phase locked loop for generation of a low jitter transmit
clock.
• A pseudo-random sequence user selectable from 27 –1, 211 –1, 215 –1 or 220 –
1, may be inserted into the E1 stream in either the ingress or egress
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS
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