PM4318-BI データシートの表示（PDF） - PMC-Sierra

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PM4318-BI

OCTAL E1/T1/J1 LINE INTERFACE DEVICE

PMC-Sierra 

PRELIMINARY

DATASHEET

PMC- 2001578

ISSUE 3

PM4318 OCTLIU

OCTAL E1/T1/J1 LINE INTERFACE DEVICE

Pin Name

DDATA[0]/RDP[1]

DDATA[1]/RDP[2]

DDATA[2]/RDP[3]

DDATA[3]/RDP[4]

DDATA[4]/RDP[5]

DDATA[5]/RDP[6]

DDATA[6]/RDP[7]

DDATA[7]/RDP[8]

DDP/RDN/RLCV[4]

DPL/RDN/RLCV[5]

Type

Tristate

Output

Tristate

Output

Tristate

Output

Pin Function

No.

AB19

Y17

AB16

AB15

W8

AA5

Y5

W5

The SBI DROP bus data signals (DDATA[7:0]) contain time

division multiplexed receive data from up to 84 independently

timed links. Link data is transported as T1 or E1 tributaries within

the SBI TDM bus structure. The OCTLIU may be configured to

insert data into up to 8 tributaries within the structure. Multiple

LIU devices can drive the SBI DROP bus at uniquely assigned

tributary column positions. DDATA[7:0] are tristated when the

OCTLIU is not outputting data on a particular tributary column.

DDATA[7:0] are updated on the rising edge of REFCLK.

DDATA[7:0] share the same pins as the RDP[8:1] outputs.

DDATA[7:0] are selected when SBI_EN or SBI2CLK is tied high.

Y14 The SBI DROP bus parity signal (DDP) carries the even or odd

parity for the DROP bus signals. The parity calculation

encompasses the DDATA[7:0], DPL and DV5 signals.

Multiple LIU devices can drive this signal at uniquely assigned

tributary column positions. DDP is tristated when the OCTLIU is

not outputting data on a particular tributary column. This parity

signal is intended to detect accidental source clashes in the

column assignment.

DDP is updated on the rising edge of REFCLK.

DDP shares the same pin as the RDN/RLCV[4] output. DDP is

selected when SBI_EN or SBI2CLK is tied high.

Y8 The SBI DROP bus payload signal (DPL) indicates valid data

within the SBI TDM bus structure. This signal is asserted during

all octets making up a tributary. This signal may be asserted

during the V3 octet within a tributary to accommodate negative

timing adjustments between the tributary rate and the fixed TDM

bus structure. This signal may be deasserted during the octet

following the V3 octet within a tributary to accommodate positive

timing adjustments between the tributary rate and the fixed TDM

bus structure.

Multiple LIU devices can drive this signal at uniquely assigned

tributary column positions. DPL is tristated when the OCTLIU is

not outputting data on a particular tributary column.

DPL is updated on the rising edge of REFCLK.

DPL shares the same pin as the RDN/RLCV[5] output. DPL is

selected when SBI_EN or SBI2CLK is tied high.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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