PM4318-BI データシートの表示（PDF） - PMC-Sierra

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PM4318-BI

OCTAL E1/T1/J1 LINE INTERFACE DEVICE

PMC-Sierra 

PRELIMINARY

DATASHEET

PMC- 2001578

ISSUE 3

PM4318 OCTLIU

OCTAL E1/T1/J1 LINE INTERFACE DEVICE

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DESCRIPTION

The PM4318 Octal E1/T1/J1 Line Interface Device (OCTLIU) is a monolithic integrated circuit

suitable for use in long haul and short haul T1, J1 and E1 systems with a minimum of external

circuitry. The OCTLIU is configurable via microprocessor control or SPI-compatible serial PROM

interface, allowing feature selection without changes to external wiring.

Analogue circuitry is provided to allow direct reception of long haul E1 and T1 compatible signals

with up to 36 dB cable loss (at 1.024 MHz) in E1 mode or up to 36 dB cable loss (at 772 kHz) in

T1 mode using a minimum of external components. Typically, only line protection, a transformer

and a line termination resistor are required.

The OCTLIU recovers clock and data from the line. Decoding of AMI, HDB3 and B8ZS line codes

is supported. In T1 mode, the OCTLIU also detects the presence of in-band loop back codes.

The OCTLIU supports detection of loss of signal, pulse density violation and line code violation

alarm conditions. Line code violations are accumulated for performance monitoring purposes.

Internal analogue circuitry allows direct transmission of long haul and short haul T1 and E1

compatible signals using a minimum of external components. Typically, only line protection, a

transformer and an optional line termination resistor are required. Digitally programmable pulse

shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect,

E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into

120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated

support for LBO filtering as required by the FCC rules. In addition, the programmable pulse

shape extending over 5-bit periods allows customization of short haul and long haul line interface

circuits to application requirements.

Each channel of the OCTLIU can generate a low jitter transmit clock from the input clock source

and also provide jitter attenuation in the receive path. A low jitter recovered T1 clock can be

routed outside the OCTLIU for network timing applications.

Serial PCM interfaces to each T1/E1 LIU allow 1.544 Mbit/s or 2.048 Mbit/s backplane

receive/backplane transmit system interfaces to be directly supported. Data may be transferred

either as dual rail line pulses or single rail DS-1/E1 data. Alternatively, the OCTLIU supports an

8-bit parallel SBI interface for interfacing to high-density framers.

The OCTLIU may be configured to operate in a mode in which the LIUs are disabled and the

device acts as a converter between the SBI interface and serial clock and data. Up to 8 serial

data streams (sharing a common clock and frame pulse) may be mapped on to the SBI bus in

this mode.

The OCTLIU may be configured, controlled and monitored via a generic 8-bit microprocessor bus

through which all internal registers are accessed. Alternatively, the device may be operated in a

‘hardware only’ mode in which no microprocessor is required. In this case, the OCTLIU reads

configuration information from an SPI-compatible serial PROM interface on power up. Multiple

OCTLIUs can be configured from a single serial PROM via a cascade interface on the OCTLIU.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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