PLL102-108XC データシートの表示（PDF） - PhaseLink Corporation

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PLL102-108XC

Programmable DDR Zero Delay Clock Driver

PhaseLink Corporation 

PLL102-108

Programmable DDR Zero Delay Clock Driver

I2C BUS CONFIGURATION SETTING

Address Assignment

A6

1

A5

1

A4

0

A3

1

A2

0

A1

0

A0

1

R/W

_

Slave Re-

ceiver/Transmitter

Provides both slave write and readback functionality

Data Transfer Rate Standard mode at 100kbits/s

Data Protocol

This serial protocol is designed to allow both blocks write and read from the controller. The

bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred

must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will termi-

nate the transfer. The write or read block both begins with the master sending a slave address

and a write condition (0xD4) or a read condition (0xD5).

Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte

Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte

Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at

power-up is = (0x09).

I2C CONTROL REGISTERS

1. BYTE 0: Outputs Register (1=Enable, 0=Disable)

Bit

Pin#

Default Description

Bit 7

39,40

1

CLKT7, CLKC7 (1= active, 0=inactive)

Bit 6

43,44

1

CLKT6, CLKC6 (1= active, 0=inactive)

Bit 5

46,47

1

CLKT5, CLKC5 (1= active, 0=inactive)

Bit 4

22,23

1

CLKT4, CLKC4 (1= active, 0=inactive)

Bit 3

19,20

1

CLKT3, CLKC3 (1= active, 0=inactive)

Bit 2

9,10

1

CLKT2, CLKC2 (1= active, 0=inactive)

Bit 1

5,6

1

CLKT1, CLKC1 (1= active, 0=inactive)

Bit 0

2,3

1

CLKT0, CLKC0 (1= active, 0=inactive)

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 03/29/02 Page 3

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