UPD78064B データシートの表示（PDF） - NEC => Renesas Technology

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UPD78064B

8-BIT SINGLE-CHIP MICROCONTROLLER

NEC => Renesas Technology 

µPD78064B(A)

FUNCTION OVERVIEW

Item

Internal

memory

ROM

High-speed RAM

LCD display RAM

General registers

Minimum When main system clock

instruction selected

execution When subsystem clock

time

selected

Instruction set

I/O ports

(including segment signal output pins)

A/D converter

LCD controller/driver

Serial interface

Timer

Timer output

Clock output

Buzzer output

Vectored

interrupt

source

Maskable

Non-maskable

Software

Test input

Supply voltage

Package

Function

32 Kbytes

1024 bytes

40 × 4 bits

8 bits × 32 registers (8 bits × 8 registers × 4 banks)

0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0-MHz operation)

122 µs (@ 32.768-kHz operation)

• 16-bit operation

• Multiply/divide (8 bits × 8 bits,16 bits/8 bits)

• Bit manipulate (set, reset, test, boolean operation)

• BCD adjust, etc.

Total

• CMOS input

• CMOS I/O

: 57

: 02

: 55

• 8-bit resolution × 8 channels

• Segment signal output : Maximum 40

• Common signal output : Maximum 4

• Bias

: 1/2 or 1/3 switchable

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel

• 3-wire serial I/O/UART mode selectable

: 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

: 1 channel

• Watchdog timer

: 1 channel

3 (14-bit PWM output capability : 1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,

5.0 MHz (@ 5.0-MHz operation with main system clock)

32.768 kHz (@ 32.768-kHz operation with subsystem clock)

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0-MHz operation with main system clock)

Internal : 12, external : 6

Internal : 1

1

Internal : 1, external: 1

VDD = 2.0 to 6.0 V

• 100-pin plastic QFP (fine pitch) (14 × 14 mm)

• 100-pin plastic LQFP (fine pitch) (14 × 14 mm)Note

• 100-pin plastic QFP (14 × 20 mm)

Note Under development

5

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