PI90LV044 データシートの表示（PDF） - Pericom Semiconductor
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PI90LV044 Datasheet PDF : 12 Pages
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PI90LV044, PI90LVB044
LVDS Dual 2x2 Crosspoint/Repeater Switch
Features
• Dual 2x2 Crosspoint/Repeater Switch
• Meets or Exceeds the Requirements of
ANSI TIA/EIA-644-1995
• Designed for Signaling Rates up to 650 Mbit/s (325Mhz)
• Operates from a single 3.3V Supply: –40°C to 85°C
• Low-Voltage Differential Signaling with Output Voltages of
±350mV into:
- 100Ω load (PI90LV044)
- 50Ω load Bus LVDS Signaling (PI90LVB044)
• Accepts ±350mV differential inputs
• Wide common mode input range: 0.2V to 2.7V
• Output drivers are high impedance when disabled or
when VCC ≤ 1.5V
• Inputs are open, short, and terminated fail safe
• Propagation Delay Time: 3.5ns
• ESD protection is 10kV on bus pins
• Bus Pins are High Impedance when disabled or
with VCC less than 1.5V
• TTL Inputs are 5V Tolerant
• Power Dissipation at 400 Mbit/s of 250mW
• Packaging (Pb-free & Green available):
- 28-pin QSOP (Q)
- 28-pin TSSOP (L)
Description
The PI90LV044 and PI90LVB044 are monolithic dual 2x2 asyn-
chronous crosspoint/repeater switches. The crosspoint function
is based on a multiplexer tree architecture. Each 2x2 switch can
be considered as a pair of 2:1 multiplexers that share the same
inputs. The signal path through each switch is fully differential
with minimal propagation delay. The signal path is unregistered,
so no clock is required for the data inputs. The signal line drivers
and receivers use Low Voltage Differential Signaling (LVDS) to
achieve signaling rates as high as 650Mbps.
The LVDS standard provides a minimum differential output volt-
age magnitude of 247 mV into a 100Ω load and receipt of 100
mV signals with up to 1V of ground potential difference between a
transmitter and receiver. The PI90LVB044 doubles the output drive
current to achieve LVDS levels with a 50 ohm load.
The intended application of these devices is for loop-through and
redundant channel switching for both point-to-point baseband
(PI90LV044) and multipoint (PI90LVB044) data transmissions
over controlled impedance media.
Pin Configuration
Block Diagram
S0,S1
1A/1B
2A/2B
3A/3B
4A/4B
S2/S3
1DE/2DE
1Y/1Z
2Y/2Z
3Y/3Z
4Y/4Z
3DE/4DE
1B
1
1A
2
S0
3
1DE
4
S1
5
2A
6
2B
7
3A
8
3B
9
S2
10
3DE
11
S3
12
4A
13
4B
14
28
VCC
27
1Y
26
1Z
25
2DE
24
2Z
23
2Y
22
GND
21
VCC
20
3Y
19
3Z
18
4DE
17
4Y
16
4Z
15
GND
1
PS8485D
09/22/04
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