PI2002-00-QEIG データシートの表示（PDF） - Vicor

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PI2002-00-QEIG

Active ORing Controller IC with Load Disconnect Feature

Vicor 

When the input source voltage is applied and before

the MOSFET is fully enhanced, a voltage greater

than the Forward Over-Current (FOC) Threshold

may be present across the MOSFET. To avoid an

erroneous FOC detection, a VGS detector blanks

the FOC and FWD comparators from initiating a

fault, until the GATE pin reaches 45% of VG-CLMP. If

VC is too low to establish the Gate Clamp condition

the reference for detection is 45% of {VC-V(SN) -

0.25V}.

The GATE pin pulls low under the following fault

conditions:

• Reverse Current

• Forward Over-Current “AND” clamp detector is

cleared

• Over Temperature

• Input Under-Voltage

• Input Over-Voltage “AND” nominal Forward

Current

• VC pin Under-Voltage

Fault:

The fault circuit output is an open collector with 40μs

delay to prevent any false triggering. The FT pin

will be pulled low when any of the following faults

occurs:

• Reverse Current

• Forward Over-Current “AND” clamp detector is

cleared

• Forward Low Current “AND” clamp detector is

cleared

• Over Temperature

• Input Under-Voltage

• Input Over-Voltage “AND” nominal Forward

Current

• VC pin Under-Voltage

The Forward Current fault condition occurs when the

MOSFETs gates are high but are not conducting a

significant level of forward current or may indicate

the MOSFETs are shorted either internally or

externally (VD1-D2 < 6mV).

The VGS detector prevents FOC or FWD from

initiating a fault when the MOSFET gate is low. The

gate to SN voltage has to reach sufficient voltage to

establish the Rds(on) condition before these faults

are detected.

Picor Corporation • picorpower.com

PI2002

Rev1.1 Page 8 of 23

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