PEB 20542
PEF 20542
List of Figures
Page
Figure 85
Figure 86
Figure 87
Figure 88
Clock Mode 5 Frame Synchronisation Timing . . . . . . . . . . . . . . . . . . 292
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . 295
Data Sheet
11
2000-09-14