PEB20532 データシートの表示（PDF） - Infineon Technologies
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PEB20532 Datasheet PDF : 282 Pages
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PEB 20532
Revision History:
Previous Version:
Page
(previous
Version)
Page
(current
Version)
32-34
35-37
80
83
214, 222 218, 226
n.a.
263, 266
n.a.
263
253
257
2000-09-14
DS 1
SEROCCO V1.1 Preliminary Data Sheet, 08.99, DS1
Subjects (major changes since last revision)
Correction: signal ’OSR’ is multiplexed with signal ’CD’, signal
’OST’ is multiplexed with ’CTS’ (was vice versa)
corrected HDLC receive address recognition table
Corrected location of TCD interrupt (async/bisync modes only)
in registers ISR0 and IMR0 from bit 7 to bit 2.
Added timing diagram for external DMA support signals
Added address timing diagram for Intel multiplexed mode
(signal ALE)
Chapter "Electrical Characteristics" updated with final
characterization results.
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
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