PE9702(2003) データシートの表示（PDF） - Peregrine Semiconductor Corp.

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PE9702
(Rev.:2003)

3.0 GHz Integer-N PLL for Rad Hard Applications

Peregrine Semiconductor Corp. 

PE9702

Advance Information

Pin No. Pin Name Interface Mode

Type

Description

31

VDD-fp

ALL

(Note 1) VDD for fp. Can be left floating or connected to GND to disable the fp output.

32

Dout

Serial, Parallel

Output

Data Out. The MSEL signal and the raw prescaler output are available on Dout through

enhancement register programming.

33

VDD

ALL

34

Cext

ALL

(Note 1)

Output

Same as pin 1.

Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series

resistor. Connecting Cext to an external capacitor will low pass filter the input to the

inverting amplifier used for driving LD.

35

VDD

ALL

36

PD_D

ALL

37

PD_U

ALL

38

VDD-fc

ALL

39

fc

ALL

40

GND

ALL

(Note 1)

Output

(Note 1)

Output

Same as pin 1.

PD_D is pulse down when fp leads fc.

PD_U is pulse down when fc leads fp.

VDD for fc. Can be left floating or connected to GND to disable the fc output.

Monitor pin for reference divider output. Switching activity can be disabled through

enhancement register programming or by floating or grounding VDD pin 38.

Ground.

41

GND

ALL

Ground.

42

fr

ALL

43

LD

ALL

Input

Output,

OD

Reference frequency input.

Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is

high impedance, otherwise LD is a logic low (“0”).

44

Enh

Serial, Parallel

Input

Enhancement mode. When asserted low (“0”), enhancement register bits are

functional.

Note 1:

Note 2:

VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.

VDD pins 31 and 38 are used to enable test modes and should be left floating.

All digital input pins have 70 kΩ pull-down resistors to ground.

Copyright  Peregrine Semiconductor Corp. 2003

Page 4 of 15

File No. 70/0036~00C | UTSi  CMOS RFIC SOLUTIONS

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