PCK2023DGG データシートの表示（PDF） - Philips Electronics

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PCK2023DGG

CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator

Philips Electronics 

Philips Semiconductors

CK408 (66/100/133/200 MHz) spread

spectrum differential system clock generator

Product data

PCK2023

ALL OUTPUTS

SYMBOL

tPZL/tPZH

tPZL/tPZH

tSTABLE

PARAMETER

output enable delay (all outputs)

output disable delay (all outputs)

all clock stabilization from power-up

LIMITS

Tamb = 0 to +70 °C

MIN

MAX

1.0

10.0

1.0

10.0

—

3

UNITS

ns

ns

ms

NOTES

11

NOTES:

1. Measured at crossing points or where subtraction of CLK-CLK crosses 0 V.

2. Measured from VOL = 0.175 V to VOH = 0.525 V.

3. These crossing points refer to only crossing points containing a rising edge of a CPU output (as opposed to a CPU output).

4. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.

5. Measured from VOL = 0.2 V to VOH = 0.8 V.

6. Determined as a fraction of 2* (tRISE–tFALL)/(tRISE+tFALL).

7. Test load is RS = 33.2 Ω, RP = 49.9 Ω.

8. Period, jitter, offset and skew measured at rising edge @ 1.5 V for 3.3 V clocks.

9. THIGH is measured at 2.4 V for non-CPU outputs.

10. TLOW is measured at 0.4 V for all outputs.

11. The time specified is measured from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency

output is stable and operating within specification.

12. The 3.3 V clock tRISE and tFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC

specification.

13. The average period over any 1 µs period of time must be greater than the minimum specified period.

14. Designed for 150–420 ps (1 V/ns minimum rise time across 0.42 V).

15. Measurement taken from differential waveform.

16. Measurement taken from differential waveform from –0.35 to +0.35 V.

17. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86 V. Rise/fall time matching is defined as “the

instantaneous difference between maximum CLK rise (fall) and minimum CLK fall (rise) time, or minimum CLK rise (fall) and maximum CLK

fall (rise) time”. This parameter is designed for waveform symmetry.

18. Measured in absolute voltage, single ended.

19. Cycle-to-cycle jitter measurements taken with minimum capacitive loading on non-CPU outputs.

2001 Sep 07

12

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