PCK2001R データシートの表示（PDF） - Philips Electronics

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PCK2001R

14.318 – 133 MHz I2C 1:6 clock buffer

Philips Electronics 

Philips Semiconductors

14.318 – 133 MHz I2C 1:6 clock buffer

Product specification

PCK2001R

SERIAL CONFIGURATION MAP

The serial bits will be read by the clock buffer in the following order:

Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 2 – Bits 7, 6, 5, 4, 3, 2, 1, 0

All unused register bits (Reserved and N/A) should be desined as “Don’t Care”. It is expected that the controller will force all of these bits to a

“0” level.

All register bits labeled “Initialize to 0” must be written to zero during intialization. Failure to do so may result in a higher than normal operating

current. The controller will read back the last written value.

Byte 0: Active/inactive register

1 = enable; 0 = disable

BIT

PIN#

NAME

DESCRIPTION

7

6

BUF_OUT7

Active/Inactive

6

—

—

—

5

—

—

—

4

—

—

—

3

—

—

—

2

3

BUF_OUT2

Active/Inactive

1

—

—

—

0

1

BUF_OUT0

Active/Inactive

NOTE:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are

not expected to be configured during the normal modes of operation.

Byte 1: Active/inactive register

1 = enable; 0 = disable

BIT

PIN#

NAME

DESCRIPTION

7

—

—

—

6

15

BUF_OUT14

Active/Inactive

5

—

—

—

4

—

—

—

3

13

BUF_OUT11

Active/Inactive

2

—

—

—

1

—

—

—

0

—

—

—

NOTE:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are

not expected to be configured during the normal modes of operation.

Byte 2: Active/inactive register

BIT

PIN#

NAME

DESCRIPTION

7

11

BUF_OUT17

Active/Inactive

6

—

—

—

5

—

—

—

4

—

—

—

3

—

—

—

2

—

—

—

1

—

—

—

0

—

—

—

NOTE:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are

not expected to be configured during the normal modes of operation.

2000 Jul 25

8

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