CXA1386K データシートの表示（PDF） - Sony Semiconductor
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CXA1386K Datasheet PDF : 21 Pages
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CXA1386P/K
Pin No
Symbol
LCC DIP
Standard
I/O voltage
level
4, 20 2, 13 DVEE — –5.2V
8
4
D0
9
5
D1
10
6
D2
11
7
D3
O
ECL
12
8
D4
13
9
D5
14
10
D6
15
11
D7
Equivalent circuit
Description
Digital VEE
Internally connected
with AVEE
(resistance: 4 to 6Ω)
Ceramic chip
capacitors of at least
0.1µF should be used
to connect to DGND
and be placed near the
pins.
DGND (DGND2) LSB of data outputs.
External pull-down
resistor is required.
Di
Data outputs.
External pull-down
resistors are required.
MSB of data outputs.
External pull-down
DVEE
resistor is required.
DGND (DGND1)
3
1 LINV
I
ECL
r
LINV
r
or
MINV
r
21
14 MINV I
ECL
DVEE
r
Input pin for D0 (LSB)
to D6 output polarity
inversion (see output
code table).
With open connection,
kept at "L" level.
–1.3V
Input pin for D7 (MSB)
output polarity
inversion (see output
code table).
With open connection,
kept at "L" level.
–5–
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