P4C1026-15L32MB データシートの表示（PDF） - Semiconductor Corporation
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P4C1026-15L32MB Datasheet PDF : 10 Pages
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TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7)
P4C1026
AC CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym. Parameter
tWC Write Cycle Time
tCW Chip Enable Time to End of Write
-15
-20
-25
-35
Unit
Min Max Min Max Min Max Min Max
13
20
25
35
ns
12
15
18
25
ns
tAW Address Valid to End of Write
12
15
18
25
ns
tAS Address Set-up Time
0
0
0
0
ns
tWP Write Pulse Width
tAH Address Hold Time from End of Write
tDW Data Valid to End of Write
tDH Data Hold Time
tWZ Write Enable to Output in High Z
tDW Output Active from End of Write
12
15
18
25
ns
0
0
0
0
ns
7
8
10
15
ns
0
0
0
0
ns
6
8
10
15
ns
2
2
2
3
ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
Document # SRAM127 REV E
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Page 5 of10
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