P4C1024-17J4C データシートの表示（PDF） - Semiconductor Corporation
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P4C1024-17J4C Datasheet PDF : 14 Pages
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TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(11)
P4C1024
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Fig. 1 and 2
TRUTH TABLE
Mode
Standby
Standby
CE1 CE2 OE WE I/O Power
H X X X High Z Standby
X L X X High Z Standby
DOUT Disabled L H H H High Z Active
Read
Write
L H L H DOUT Active
L H X L High Z Active
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1024, care must be
taken when testing this device; an inadequate setup can cause a
normal functioning part to be rejected as faulty. Long high-
inductance leads that cause supply bounce must be avoided by
bringing the VCC and ground planes directly up to the contactor
fingers. A 0.01 µF high frequency capacitor is also required
between VCC and ground.
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω load
with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω
resistor must be used in series with DOUT to match 166Ω (Thevenin
Resistance).
Document # SRAM124 REV A
Page 7 of 14
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