P4C1024-17J4I データシートの表示（PDF） - Semiconductor Corporation
部品番号
コンポーネント説明
一致するリスト
P4C1024-17J4I Datasheet PDF : 14 Pages
| |||
TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
P4C1024
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10)
Notes:
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether CE1 or CE2 causes them.
Document # SRAM124 REV A
Page 5 of 14
Share Link: 