STK301-220 データシートの表示（PDF） - SANYO -> Panasonic

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STK301-220

7-band, 2-channel Electronic Graphic Equalizer

SANYO -> Panasonic 

STK301-220

With the STK301-220, few crossover bands exist with an increase in swell during total boost. Pass-band-ripple

(P.B.R.) width at this time is 4 dB with Q set at 3.5 fore and aft.

Data Code

1. Turning on the power initiates a process which transmits no

data (0) for 60 clock cycles (initialization clock). When data

is stopped en route, the remaining data is sent only after the

clock has been initialized.

2. Using DI and CLK in conjunction with LC75821 (or

equivalent) involves the transmission of the maximum

initialization clock to those devices involved.

Things to Note

1. A 1000pF rated capacitor (or higher) should be installed between the current pin and VSS.

2. When the control signal on the microcontroller side onsets faster than STK301-220’s VDD, a resistor rated at

2 kΩ or more should be placed on the DI and CLK line.

3. Since the STK301-220 is equipped with a built-in CMOS LSI, sufficient caution should be extended to damage

caused by static electricity.

4. Refer to the specification sheet for itemized details about the LC7522.

No. 4793-7/8

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