NJU3503L データシートの表示（PDF） - Japan Radio Corporation
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NJU3503L Datasheet PDF : 60 Pages
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NJU3503
Mnemonic
Operation
code
Function
Status Cycle
Memo
JPL addr 68−6F ST=1:PC←addr, ST=0:No branch
1
2 2byte Mnemonic
JMP addr C0−FF ST=1:PC←addr, ST=0:No branch
1
1
CALL addr 60−67 ST=1:(SP)←PC+2, SP←SP+1, PC←addr 1
2 2byte Mnemonic
ST=0:No branch
RET
2B PC←(SP), SP←SP-1
1
1
RETI
2C PC←(SP), AC←(SP), SP←SP-1
∗
1
X←(SP), X’←(SP), Y←(SP), Y’ ←(SP)
RPC← (SP), ST← (SP)
SBIT b
RBIT b
TBIT b
TBA b
RAR
30−33
34−37
38−3B
3C−3F
21
M(X,Y)b←1
M(X,Y)b←0
ST←M(X,Y)b
ST←(AC)b
CY
AC
b3 b2 b1 b0
1
1 B=0−3
1
1 B=0−3
∗
1 B=0−3
∗
1 B=0−3
∗
1
RAL
22
AC
∗
1
CY
b3 b2 b1 b0
RYR
24
Y
CY
b3 b2 b1 b0
∗
1 RPC=0
Y’
CY
b3 b2 b1 b0
∗
1 RPC=1
RYL
25
Y
∗
1 RPC=0
CY
b3 b2 b1 b0
Y’
CY
b3 b2 b1 b0
∗
1 RPC=1
RXR
28
X
CY
b3 b2 b1 b0
∗
1 RPC=0
X’
CY
b3 b2 b1 b0
∗
1 RPC=1
RXL
29
X
∗
1 RPC=0
CY
b3 b2 b1 b0
X’
CY
b3 b2 b1 b0
∗
1 RPC=1
SEC
CLC
SRPC
RRPC
NOP
HLT
MDT
0C CY←1
1C CY←0
10 RPC←1
20 RPC←0
00 No Operation
07 CPU Halted
06 Memory Dump Test
1
1
0
1
1
1
1
1
1
1
1
1
−
−
Note)
←
∧
∨
⊕
+
-
<>
:Transfer direction
:AND
:OR
:Exclusive OR
:Add
:Subtraction
:Comparison
AC
X
X’
Y
Y’
PH
M
ROM
PC
:Accumulator
:Xregister
:X’register
:Yregister
:Y’register
:Peripheral register
:Data memory
:Program memory
:Program counter
SP
RPC
CY
ST
#K
addr
()
b
:Stack pointer
:RPC flag
:Carry flag
:Status flag
:Immediate data
:Blanch address
:A content of register or memory
pointed by the address indicated in ( ).
:Bit position
Status description)
0:After the command execution, ST-flag is always set to “0”.
1:After the command execution, ST-flag is always set to “1”.
∗:Status
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