NB2309AI1HDG(2015) データシートの表示（PDF） - ON Semiconductor

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NB2309AI1HDG
(Rev.:2015)

3.3 V Zero Delay Clock Buffer

ON Semiconductor 

NB2309A

REF

PLL

MUX

CLKOUT

CLKA1

CLKA2

CLKA3

S2

SELECT INPUT

DECODING

S1

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Figure 1. Block Diagram

Table 1. SELECT INPUT DECODING

CLKOUT

PLL

S2

S1

Clock A1 − A4

Clock B1 − B4

(Note 1)

Output Source

ShutDown

0

0

Three−state

Three−state

Driven

PLL

N

0

1

Driven

Three−state

Driven

PLL

N

1

0

Driven

Driven

Driven

Reference

Y

1

1

Driven

Driven

Driven

PLL

N

1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the

reference and the output.

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2

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