74F393 データシートの表示（PDF） - Philips Electronics
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74F393 Datasheet PDF : 8 Pages
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Philips Semiconductors
Dual 4-bit binary ripple counter
Product specification
74F393
FEATURES
• Two 4-bit binary counters
• Two Master Resets to clear each 4-bit counter individually
DESCRIPTION
The 74F393 is a Dual Ripple Counter with separate Clock (CPn) and
Master Reset (MR) inputs to each counter. The two counters are
identified by the “a” and “b” suffixes in the pin configuration. The
operation of each half of the 74F393 is the same. The counters are
triggered by a High-to-Low transition of the Clock (CPa and CPb)
inputs. The counter outputs are internally connected to provide
Clock inputs to succeeding stages. The outputs of the ripple counter
do not change synchronously and should not be used for high speed
address decoding. The Master Resets (MRa and MRb) are active
High asynchronous inputs; one for each 4-bit counter. A High level
in the MR input overrides the Clock and sets the outputs Low.
PIN CONFIGURATION
CPa 1
MRa 2
Q0a 3
Q1a 4
Q2a 5
Q3a 6
GND 7
14 VCC
13 CPb
12 MRb
11 Q0b
10 Q1b
9 Q2b
8 Q3b
SF00704
TYPE
74F393
TYPICAL fMAX
125MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
40mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
14-pin plastic DIP
N74F393N
14-pin plastic SO
N74F393D
PKG DWG #
SOT27-1
SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
CPa, CPb
Clock inputs
1.0/1.0
MRa, MRb
Master Reset inputs
1.0/1.0
Qna – Qnb
Data outputs
50/33.3
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE HIGH/LOW
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
LOGIC SYMBOL
IEC/IEEE SYMBOL (IEEE/IEC)
1
CPa
13
CPb
2
MRa
12
MRb
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
3 4 5 6 11 10 9 8
VCC = Pin 14
GND = Pin 7
SF00705
CTR DIV 16
2
3
CT=0
0
1
4
+
5
6
3
CTR DIV 16
11
12
0
CT=0
10
13
+
9
8
3
SF00706
1988 Nov 01
2
853–0295 94977
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