MXC6202XK データシートの表示（PDF） - Unspecified

部品番号

コンポーネント説明

一致するリスト

MXC6202XK

Ultra Low Cost, ±2.0 g Dual Axis Accelerometer With I2C Interface

Unspecified 

given to the MEMSIC device to return from a power-

down mode. The delay value depends on the type of

MEMSIC device. Generally speaking, low power

products tend to have longer startup time.

Fourth cycle: The master device sends a START

command followed by calling MEMSIC device address

with a WRITE (8th SCL, SDA keep low). An

“acknowledge” should be sent by the MEMSIC device

at the end.

Fifth cycle: The master device writes to the MEMSIC

device a “[00000000]” as the starting address for

which internal memory is to be read. Since

“[00000000]” is the address of internal control register,

reading from this address can serve as a verification

of operation and to confirm the write command has

been successful. Note: the starting address in

principle can be any of the 5 addresses. For example,

user can start read from address “[0000001]”, which is

X channel MSB.

Sixth cycle: The master device calls the MEMSIC

device address with a READ (8th SCL cycle SDA line

high). The MEMSIC device should acknowledge at

the end.

Seventh cycle: The master device cycles the SCL

line, first addressed memory data appears on SDA

line. If in step 7, “[00000000]” was sent, internal

control register data should appear (in the following

steps, this case is assumed). The master device

should send an acknowledgement at the end.

Eighth cycle: The master device continues to cycle

the SCL line, the next byte of internal memory should

appear on the SDA line (MSB of X channel). The

internal memory address pointer automatically moves

to the next byte. The master acknowledges.

Ninth cycle: LSB of X channel. In the case that the

TOEN bit of internal register was set to “1”, the MSB

and LSB of TOUT (temperature) should appear in the

last two steps.

Tenth cycle: MSB of Y channel.

Eleventh cycle: LSB of Y channel.

The master ends communications by sending a NO

acknowledge and followed by a STOP command.

Note: if the master device continues to cycle the SCL

line, the memory pointer will go to sixth and seventh

positions, which always have “[00000000]”. After

seventh position, pointer will go to zero again.

Optional: The master powers down the MEMSIC

device by writing into the internal control register. (See

step 1 through 4 for WRITE operation)

MEMSIC MXC6202xJ/K Rev.A

Page 10 of 11

3/20/2006

Share Link: