MT9M001 データシートの表示（PDF） - Micron Technology

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MT9M001

1/2-Inch Megapixel CMOS Digital Image Sensor

Micron Technology 

MT9M001 - 1/2-Inch Megapixel Digital Image Sensor

Serial Bus Description

Slave Address

The 8-bit address of a two-wire serial interface device consists of seven bits of address

and 1 bit of direction. A “0” (0xBA) in the LSB (least significant bit) of the address indi-

cates the write mode, and a “1” (0xBB) indicates read mode.

Data Bit Transfer

One data bit is transferred during each clock pulse. The serial interface clock pulse is

provided by the master. The data must be stable during the HIGH period of the two-wire

serial interface clock—it can only change when the serial clock is LOW. Data is trans-

ferred eight bits at a time, followed by an acknowledge bit.

Acknowledge Bit

The master generates the acknowledge clock pulse. The transmitter (which is the master

when writing, or the slave when reading) releases the data line, and the receiver indi-

cates an acknowledge bit by pulling the data line LOW during the acknowledge clock

pulse.

No-Acknowledge Bit

The no-acknowledge bit is generated when the data line is not pulled down by the

receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate

a read sequence.

80a3e031

MT9M001_DS_2.fm - Rev.C 7/05 EN

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2004 Micron Technology, Inc. All rights reserved.

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