1Semiconductor
FEDL9225B-03
MSM9225B
AC Characteristics
Parallel mode
Parameter
Symbol
(VDD = 4.5 to 5.5 V, Ta = –40 to +125°C, fOSC = 16 MHz)
Condition
Min.
Max.
Unit
ALE Address Setup Time
tAS
—
ALE Address Hold Time
tAH
—
PRD Output Data Delay Time
tRDLY
—
10
—
ns
10
—
ns
—
60*1
ns
PRD Output Data Hold Time
tRDH
—
ALE “H” Level Width
tWALEH
—
When PRDY is not
Access Cycle generated
When PRDY is
tcyc
—
generated
5
—
ns
16.5
—
ns
4T
—
ns
7T
—
ns
Address Hold Time from PRD
tRAH
—
ALE Delay Time from PRD
tHRA
—
PRD “H” Level Width
tWRDH
—
PRDY “L” Delay Time
tARLDLY
—
PRDY “L” Level Width
tWRDYL
—
Data Output Delay Time from PRDY
tARDDLY
—
PWR Hold Time from PRDY
tARWDLY
—
Input Data Setup Time
Input Data Hold Time
PRD Delay Time
tWDS
—
tWDH
—
tRS
—
PWR Delay Time
tWS
—
Address Hold Time from PWR
tWAH
—
ALE Delay Time from PWR
tHWA
—
PWR “H” Level Width
tWRH
—
PWR “L” Level Width
tWRL
—
0
—
ns
27
—
ns
27
—
ns
—
35
ns
0
2.5T
ns
—
35
ns
10
—
ns
30
—
ns
4
—
ns
10
—
ns
10
—
ns
10
—
ns
27
—
ns
40
—
ns
20*1
—
ns
CS Delay Time from PRD
CS Delay Time from PWR
tHRC
—
0
tHWC
—
0
The values with *1 indicate those when PRDY is not generated.
—
ns
—
ns
T = 1/fOSC
The values with *1 when PRDY is generated are defined by “Data Output Delay Time from PRDY”
tARDDLY and “PWR Hold Time from PRDY” tARWDLY.
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