MSM7728 データシートの表示（PDF） - Oki Electric Industry

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MSM7728

Single Rail Linear CODEC

Oki Electric Industry 

¡ Semiconductor

MSM7728

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Storage Temperature

Symbol

VDD

VAIN

VDIN

TSTG

Condition

AG = DG = 0 V

AG = DG = 0 V

AG = DG = 0 V

—

Rating

Unit

–0.3 to +7.0

V

–0.3 to VDD + 0.3

V

–0.3 to VDD + 0.3

V

–55 to +150

°C

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Operating Temperature

Analog Input Voltage

Symbol

Condition

VDD

—

Ta

—

VAIN Gain = 1

High Level Input Voltage

Low Level Input Voltage

VIH SYNC, BCLK, PCMIN, WRN,

RDN, DCLK, CDIN, RSTN

VIL

Min.

2.5

–30

—

0.45 ¥

VDD

0

Typ.

3.0

+25

—

—

—

Max.

3.6

+85

1.4

Unit

V

°C

VPP

VDD

V

0.16 ¥

V

VDD

Clock Frequency

FC BCLK

14 ¥ Fs — 128 ¥ Fs kHz

Sync Pulse Frequency

FS SYNC

4.0

8.0

Clock Duty Ratio

DC BCLK

40

50

Digital Input Rise Time

tIr SYNC, BCLK, PCMIN, WRN,

—

—

Digital Input Fall Time

tIf RDN, DCLK, CDIN, RSTN

—

—

Sync Signal Timing

tXS BCLKÆSYNC, See Fig.1

tSX SYNCÆBCLK, See Fig.1

100

—

100

—

High Level Sync Pulse Width *1 tWSH SYNC, See Fig.1

1 BCLK —

Low Level Sync Pulse Width *1 tWSL SYNC, See Fig.1

1 BCLK —

PCMIN Setup Time

tDS Refer to Fig.1

100

—

PCMIN Hold Time

tDH Refer to Fig.1

100

—

Digital Output Load

RDL Pull-up resistor

CDL

—

0.5

—

—

—

DCLK Pulse Width

tWCL DCLK Low width, See Fig.2

50

—

tWCH DCLK High width, See Fig.2

50

—

tWR1 DCLKÆWRNL, See Fig.2

50

—

WRN Timing

tWR2 WRNLÆDCLK, See Fig.2

tWR3 DCLKÆWRNH, See Fig.2

50

—

50

—

tWR4 WRNHÆDCLK, See Fig.2

50

—

WRN Period

PWRN

—

9DCLK —

12 kHz

60

%

50

ns

50

ns

—

ns

—

ns

—

—

—

—

—

ns

—

ns

—

kW

100 pF

—

ns

—

—

ns

—

—

ns

—

—

—

*1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is

2048 kHz.

8/23

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