MSM7716P データシートの表示（PDF） - Oki Electric Industry

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MSM7716P

Single Rail Linear CODEC

Oki Electric Industry 

OKI Semiconductor

FEDL7716P-01

MSM7716P

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Storage Temperature

Symbol

VDD

VAIN

VDIN

TSTG

Condition

AG = DG = 0 V

AG = DG = 0 V

AG = DG = 0 V

—

Rating

Unit

–0.3 to +7.0

V

–0.3 to VDD +0.3

V

–0.3 to VDD +0.3

V

–55 to +150

°C

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Operating Temperature

Analog Input Voltage

High Level Input Voltage

Low Level Input Voltage

Symbol

Condition

VDD

—

Ta

—

VAIN Gain = 1

VIH SYNC, BCLK, PCMIN, PDN,

DEN, DCLK, CDIN

VIL

Min.

3.0

–40

—

0.45×VD

D

0

Clock Frequency

Sync Pulse Frequency

FC BCLK

FS SYNC

14 × FS

4.0

Clock Duty Ratio

DC BCLK

40

Digital Input Rise Time

Digital Input Fall Time

Sync Pulse Setting Time

High Level Sync Pulse Width *1

tlr

tlf

tXS, tRS

tSX, tSR

tWSH

SYNC, BCLK, PCMIN, PDN,

DEN, DCLK, CDIN

BCLK → SYNC, See Fig. 1

SYNC → BCLK, See Fig. 1

SYNC, See Fig. 1

—

—

100

100

1 BCLK

Low Level Sync Pulse Width *1

tWSL SYNC, See Fig. 1

1 BCLK

PCMIN Setup Time

tDS Refer to Fig. 1

100

PCMIN Hold Time

tDH Refer to Fig. 1

100

Digital Output Load

DCLK Pulse Width

DEN Setting Time 1

DEN Setting Time 2

CDIN Setup Time

RDL Pull-up resistor

0.5

CDL

—

—

tWCL DCLK Low width, See Fig. 2

50

tWCH DCLK High width, See Fig. 2 50

tCDL DCLK → DEN, See Fig. 2

50

tDCL DEN → DCLK, See Fig. 2

50

tCDH DCLK → DEN, See Fig. 2

50

tDCH DEN → DCLK, See Fig. 2

50

tCDS See Fig. 2

50

CDIN Hold Time

tCDH See Fig. 2

50

Transmit gain stage, Gain = 0 dB –100

Analog Input Allowable DC Offset Voff

Transmit gain stage, Gain = 20 dB

–10

Allowable Jitter Width

— SYNC, BCLK

—

Typ.

3.3

+25

—

—

—

—

8.0

50

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Max. Unit

3.6

V

+85 °C

1.4

VPP

VDD

V

0.16×VD V

D

128 × FS kHz

16 kHz

60

%

50

ns

50

ns

—

ns

—

ns

—

—

—

—

—

ns

—

ns

—

kΩ

100 pF

—

ns

—

—

ns

—

—

ns

—

—

ns

—

+100 mV

+10 mV

1000 ns

*1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is 2048 kHz.

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