MSM7716P データシートの表示（PDF） - Oki Electric Industry

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MSM7716P

Single Rail Linear CODEC

Oki Electric Industry 

OKI Semiconductor

FEDL7716P-01

MSM7716P

TIMING DIAGRAM

PCM Data Output Timing

Transmit Timing

BCLK

tXS

SYNC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tSX

tWSH

tWSL

tXD1

PCMOUT

tSD

tXD2

tXD3

MSD D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14

When tXS ≤ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1.

When tSX < 1/2 • Fc, the Delay of the MSD bit is defined as tSD.

Receive Timing

BCLK

tRS

SYNC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

tSR

tWSH

tWSL

PCMIN

tDS

tDH

MSD D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14

Figure 1 Basic Timing Diagram

MCU Interface Timing

DCLK

tCDL

DEN

CDIN

12

tDCL

345

tWCL tWCH

678

tCDH

9 10 11 12 13

tDCH

tCDS

tCDH

B7 B6 B5 B4 B3 B2 B1 B0

Figure 2 MCU Interface Timing Diagram

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