MSM7581 データシートの表示（PDF） - Oki Electric Industry

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MSM7581

ITU-T G.721 4ch ADPCM TRANSCODER

Oki Electric Industry 

¡ Semiconductor

MSM7581

NOTES ON USAGE

(1) Through Mode (CODER Side)

t0

t1

BCLK 1 2 3 4 5 6 7 8

PCM side SYNC (SYXP)

PCM Input (SIP)

PCMDATA1

Internal Latch Timing

(A)

ADPCM side SYNC (SYXA)

Through-Data Output (SOA)

ADPCMDATA0

PCMDATA2

ADPCMDATA1

PCMDATA3

ADPCMDATA2

(B)

ADPCM side SYNC (SYXA)

Through-Data Output (SOA)

ADPCMDATA0

ADPCMDATA1

*t1 is the falling edge of the 8th BCLK counted from t0.

(A) When SYXA rises after t1, PCMDATA1 is output to ADPCMDATA1.

(B) When SYXA rises before t1, PCMDATA1 is output to ADPCMDATA1.

If SYXA rises near the t1 and jitter occurs, data slip may occur. Therefore SYXA should not rise in the range of ±500ns from t1.

The data slip means that data is deleted or the same data is output twice.

(2) Through Mode (DECODER Side)

t0

t1

BCLK 1 2 3 4 5 6 7 8

ADPCM side SYNC (SYRA)

ADPCM Input (SIA)

ADPCMDATA1

Internal Latch Timing

(A)

PCM side SYNC (SYRP)

Through-Data Output (SOP)

PCMDATA0

ADPCMDATA2

PCMDATA1

ADPCMDATA3

PCMDATA2

(B)

PCM side SYNC (SYRP)

Through-Data Output (SOP)

PCMDATA0

PCMDATA1

*t1 is the falling edge of the 8th BCLK counted from t0.

(A) When SYRP rises after t1, ADPCMDATA1 is output to PCMDATA1.

(B) When SYRP rises before t1, ADPCMDATA1 is output to PCMDATA1.

If SYRP rises near the t1 and jitter occurs, data slip may occur. Therefore SYRP should not rise in the range of ±500ns from t1.

The data slip means that data is deleted or the same data is output twice.

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