MP1530DM-LF-Z データシートの表示（PDF） - Monolithic Power Systems
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MP1530DM-LF-Z Datasheet PDF : 15 Pages
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MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS
The positive linear regulator (GH) is then soft-
started and allowed to settle in one period of CT
ramp. Nine periods of the CT ramp have
occurred since the chip enabled. If all outputs
are in regulation (>80%), the CT will stop
ramping and be held at ground.
The RDY pin will be pulled down to an active
low. If any output remains below regulation
(<80%) before and through the nine CT periods,
RDY will remain high and CT will begin its fault
timer pulse.
VGH
OUTPUT
VOLTAGES
VIN
0V
VIN
IN
0V
VEN HIGH
EN
0V
1.25V
CT
0V
VIN
RDY
0V
VMAIN
VGL
POWER ON RESET
START 1
START 2
START 3
TIME
Figure 2—Startup Timing Diagram
MP1530 Rev. 1.4
www.MonolithicPower.com
9
5/19/2006
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