OKI Semiconductor
FEDL7055-02
ML7055
CLK and Configuration
Internal
Pin Name
Direc-
tion
Pull Up/
Down,
Schmitt
SCLKP
I
—
SCLKN
O
—
XC32KP
I
—
XC32KN
O
—
SCLKSEL
I
Pull
down
SFRQSEL I
Pull
down
RFSEL0–
I
—
2
RESET
DETACH
SCL
SDA
CLKOUT
I
Schmitt
I
Schmitt
O
—
I/O
—
O
—
Initial
Value
—
—
—
—
—
—
—
—
—
L
H
—
Pin Placement
ML7055
HB
E1
D1
A2
A3
ML7055
LA
E9
E10
A9
A8
ML7055
LP
F8
F10
A9
B8
B3
A7
B7
C4
B7
A7
[*1]
[*2]
[*3]
C3
F10
G10
F2
G9
G8
G4
K7
H7
F4
J7
K7
G3
J8
K8
Description
System clock (12/13 MHz) pins
(Power level: CMOS level)
Subclock pins (for oscillator)
System clock frequency select pin
L: Select CLK divided by
internal PLL
H: Select subclock
System clock frequency select pin
L: 13 MHz
H: 12 MHz
RF-LSI select pins
RFSEL[2:0]
001: ML7050 (OKI)
010: CX72303 (SKYWORKS)
101: BCM2002X
(BROADCOM)
Others: Unused
Hardware reset pin (Reset = L)
Sleep pin (Sleep = L)
I2C serial clock
I2C serial data
System clock (12/13 MHz) output
pins
[*1] RFSEL0: E3; RFSEL1: E4; RFSEL2: H1
[*2] RFSEL0: H9; RFSEL1: H10; RFSEL2: K10
[*3] RFSEL0: H10; RFSEL1: H8; RFSEL2: K10
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