OKI Semiconductor
FEDL7055-02
ML7055
• Timing in Long Mode and in PCMCLK and PCMSYNC Output mode
(For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(O)
64k/128kHz
PCMOUT
PCMIN
PCMSYNC(O)
MSB
DATA
DATA
DATA
DATA
LSB
Data is output on the rising edge of CLK Data is shifted in on the falling edge of CLK
MSB
DATA
DATA
DATA
DATA
LSB
MSB
MSB
PCMCLK period × 3
125µs (8kHz)
• Timing in Long Mode and in PCMCLK and PCMSYNC Input Mode.
(For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(I)
64k/128kHz
PCMOUT
PCMIN
MSB
DATA
DATA
DATA
DATA
LSB
Data is output on the rising edge of CLK. Data is shifted in on the falling edge of CLK.
MSB
DATA
DATA
DATA
DATA
LSB
MSB
MSB
≥ PCMCLK period (Min.) or ≤ 62.5 µs (Max.)
125µs (8kHz)
DATA
DATA
DATA
DATA
DETACH Interface Block
• Generation of the request for change to (from) the stop mode by detection of the rising (falling) edge of
the DETACH signal
15/30