MK1707 データシートの表示（PDF） - Integrated Circuit Systems

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MK1707

Low EMI Clock Generator

Integrated Circuit Systems 

MK1707

Low EMI Clock Generator

External Components

The MK1707 requires a minimum number of external

components for proper operation.

Decoupling Capacitor

A decoupling capacitor of 0.01µF must be connected

between VDD and GND on pins 2 and 3, as close to

these pins as possible. For optimum device

performance, the decoupling capacitor should be

mounted on the component side of the PCB. Avoid the

use of vias in the decoupling circuit.

Series Termination Resistor

When the PCB trace between the clock output and the

load is over 1 inch, series termination should be used.

To series terminate a 50Ω trace (a commonly used

trace impedance), place a 33Ω resistor in series with

the clock line, as close to the clock output pin as

possible. The nominal impedance of the clock output is

20Ω.

Tri-level Select Pin Operation

The S1, S0 select pins are tri-level, meaning they have

three separate states to make the selections shown in

the table on page 2. To select the M (mid) level, the

connection to these pins must be eliminated by either

floating them originally, or tri-stating the GPIO pins

which drive the select pins.

PCB Layout Recommendations

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

1) The 0.01µF decoupling capacitor should be mounted

on the component side of the board as close to the

VDD pin as possible. No vias should be used between

the decoupling capacitor and VDD pin. The PCB trace

to VDD pin should be kept as short as possible, as

should the PCB trace to the ground via.

2) To minimize EMI, the 33Ω series termination resistor

(if needed) should be placed close to the clock output.

3) An optimum layout is one with all components on the

same side of the board, minimizing vias through other

signal layers. Other signal traces should be routed

away from the MK1707. This includes signal traces just

underneath the device, or on layers adjacent to the

ground plane layer used by the device.

Powerup Considerations

To insure proper operation of the spread spectrum

generation circuit, some precautions must be taken

while utilizing the MK1707.

1. An input signal should not be applied to ICLK until

VDD is stable (within 10% of its final value). This

requirement can easily be met by operating the

MK1707 and then ICLK source from the same power

supply.

2. LEE should not be enabled (taken high) until after

the power supplies and input clock are stable. This

requirement can be met by direct control of LEE by

system logic - for example, a “power good” signal.

Another solution is to leave LEE unconnected to

anything but a 0.01µF capacitor to ground. The internal

pullup resistor on LEE will charge the capacitor and

provide approximately a 700µs delay until spread

spectrum is enabled.

3. If the input frequency is changed during operation,

disable spread spectrum until the input clock stabilizes

at the new frequency.

MDS 1707 G

3

Revision 032204

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

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