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MC10E151FNG(2016) データシートの表示(PDF) - ON Semiconductor

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MC10E151FNG
(Rev.:2016)
ON-Semiconductor
ON Semiconductor ON-Semiconductor
MC10E151FNG Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
MC10E151, MC100E151
Table 8. AC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = 5.0 V (Note 1))
0°C
25°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min
fMAX
TPLH
tPHL
ts
Maximum Toggle Frequency
Propagation Delay to Output
CLK, MR
Setup Time
D
900 1100
900 1100
900
575 650 900 575 650 900 575
0 175
0 175
0
th
Hold Time
D
350 175
350 175
350
tRR
Reset Recovery Time
tPW
Minimum Pulse Width
CLK, MR
750 550
750 550
750
400
400
400
tSKEW
tJITTER
tr, tf
Within-Device Skew (Note 2)
Random Clock Jitter (RMS)
Rise/Fall Times
(20 - 80%)
65
65
<1
<1
300 450 700 300 450 700 300
85°C
Typ
1100
650
175
175
550
65
<1
450
Max
900
700
Unit
MHz
ps
ps
ps
ps
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. 10 Series: VEE can vary 0.46 V / +0.06 V.
100 Series: VEE can vary 0.46 V / +0.8 V.
2. Within-device skew is defined as identical transitions on similar paths through a device.
Q
Driver
Device
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D ECLinPSt I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
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