NLV74HC03ADG(2013) データシートの表示（PDF） - ON Semiconductor

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NLV74HC03ADG
(Rev.:2013)

Quad 2-Input NAND Gate with Open-Drain Outputs

ON Semiconductor 

MC74HC03A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VCC DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vout DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Iin

DC Input Current, per Pin

± 20

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Iout DC Output Current, per Pin

± 25

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ICC DC Supply Current, VCC and GND Pins

± 50

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ PD Power Dissipation in Still Air

SOIC Package†

500

mW

TSSOP Package†

450

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Tstg Storage Temperature

–65 to + 150

°C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TL Lead Temperature, 1 mm from Case for 10 Seconds

°C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SOIC or TSSOP Package

260

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress

ratings only. Functional operation above the Recommended Operating Conditions is not implied.

Extended exposure to stresses above the Recommended Operating Conditions may affect device

reliability.

†Derating − SOIC Package: – 7 mW/°C from 65° to 125°C

TSSOP Package: − 6.1 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol

Parameter

Min

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VCC DC Supply Voltage (Referenced to GND)

2.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TA Operating Temperature, All Package Types

–55

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tr, tf Input Rise and Fall Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 1)

VCC = 2.0 V

0

VCC = 4.5 V

0

VCC = 6.0 V

0

Max Unit

6.0

V

VCC

V

+125 °C

1000 ns

500

400

DESIGN GUIDE

Criteria

Internal Gate Count*

Internal Gate Propagation Delay

Internal Gate Power Dissipation

Speed Power Product

*Equivalent to a two−input NAND gate

Value

Unit

7.0

ea

1.5

ns

5.0

mW

0.0075

pJ

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

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