33291 データシートの表示（PDF） - Motorola => Freescale
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33291 Datasheet PDF : 24 Pages
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Freescale Semiconductor, Inc.
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Digital Interface Timing
Required Low State Duration for Reset (VIL < 0.2 VDD) (Note 31)
tW(RST)
—
50
167
ns
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
tLEAD
—
50
167
ns
Falling Edge of SCLK to Rising Edge of CS (Required for Setup Time)
tLAG
—
50
167
ns
SI to Falling Edge of SCLK (Required for Setup Time)
tSI(SU)
—
25
83
ns
Falling Edge of SCLK to SI (Required for Hold Time)
tSI(HOLD)
—
25
83
ns
SO Rise Time (CL = 200 pF)
tR(SO)
—
25
50
ns
SO Fall Time (CL = 200 pF)
tF(SO)
—
25
50
ns
SI, CS, SCLK, Incoming Signal Rise Time (Note 32)
tR(SI)
—
—
50
ns
SI, CS, SCLK, Incoming Signal Fall Time (Note 32)
tF(SI)
—
—
50
ns
Time from Falling Edge of CS to SO Low Impedance (Note 33)
tSO(EN)
—
—
110
ns
Time from Rising Edge of CS to SO High Impedance (Note 34)
tSO(DIS)
—
—
110
ns
Time from Rising Edge of SCLK to SO Data Valid (Note 35)
0.2 VDD < SO > 0.8 VDD, CL = 200 pF
tVALID
ns
—
65
105
Notes:
31. RST Low duration measured with outputs enabled and going to OFF or disabled condition.
32. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
33. Time required for output status data to be available for use at the SO pin.
34. Time required for output status data to be terminated at the SO pin.
35. Time required to obtain valid data out from SO following the rise of SCLK. See (Note 4).
MOTOROLA ANALOG INTEGRATED CIRFCoUIrTMDEoVrICeEIDnAfoTArmation On This Product,
Go to: www.freescale.com
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