33291 データシートの表示（PDF） - Motorola => Freescale

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33291

Eight Output Switch with Serial Peripheral Interface I/O

Motorola => Freescale 

Freescale Semiconductor, Inc.

Electrical Performance Curves

SCLK

VDD = 5.0 V

33291

Under

Test

SO

CL = 200 pF

CL represents the total capacitance of the test fixture and probe.

Figure 3. Valid Data Delay Time and

Valid Time Test Circuit

VDD = 5.0 V

VPull-Up = 2.5 V

33291

CS

Under

Test

RL = 1.0 kΩ

SO

CL = 20 pF

CL represents the total capacitance of the test fixture and probe.

Figure 4. Enable and Disable Time Test Circuit

SCLK

tr (SI)

< 50 ns

0.7 VDD

50%

tdly(lh)

SO

(Low-to-High)

SO

(High-to-Low)

0.2 VDD

tvalid

0.7 VDD

tr (SO)

tf (SO)

tdly(hl)

tf (SI)

< 50 ns

5.0 V

0.7 VDD

0.2 VDD 0

V0H

V0L

V0H

0.2 VDD

V0L

SO (Low-to-High) is for an output with internal conditions such that the

low-to-high transition of CS causes the SO output to switch from high

to low.

Figure 5. Valid Data Delay Time and

Valid Time Waveforms

CS

0.2 VDD

tr(SI)

< 50 ns

90%

10%

tf(SI)

< 50 ns

0.7 VDD

5.0 V

0

SO

(High-to-Low)

SO

(Low-to-High)

tSO(en)

90%

tSO(en)

10%

tSO(dis)

VTri-State

10%

tSO(dis)

90%

tSO(dis)

V0H

VTri-State

1. SO (high-to-low) waveform is for SO output with internal conditions such that

SO output is low except when an output is disabled as a result of detecting a

circuit fault with CS in a High Logic state, e.g. open load.

2. SO (low-to-high) waveform is for SO output with internal conditions such that

SO output is high except when an output is disabled as a result of detecting a

circuit fault with CS in a High Logic state, e.g. shortened load.

Figure 6. Enable and Disable Time Waveforms

33291

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