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MC145193

1.1 GHZ PLL FREQUENCY SYNTHESIZER

Motorola => Freescale

MC145193 Datasheet PDF : 24 Pages

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MC145193

PDout

Single–Ended Phase/Frequency Detector Output (Pin 6)

This is a three–state current–source/sink output for use as

a loop error signal when combined with an external low–pass

filter. The phase/frequency detector is characterized by a

linear transfer function. The operation of the

phase/frequency detector is described below and is shown in

Figure 17.

POL bit (C7) in the C register = low (see Figure 14)

Frequency of fV > fR or Phase of fV Leading fR:

current–sinking pulses from a floating state

Frequency of fV < fR or Phase of fV Lagging fR:

current–sourcing pulses from a floating state

Frequency and Phase of fV = fR: essentially a floating

state; voltage at pin determined by loop filter

POL bit (C7) = high

Frequency of fV > fR or Phase of fV Leading fR:

current–sourcing pulses from a floating state

Frequency of fV < fR or Phase of fV Lagging fR:

current–sinking pulses from a floating state

Frequency and Phase of fV = fR: essentially a floating

state; voltage at pin determined by loop filter

This output can be enabled, disabled, and inverted via the

C register. If desired, PDout can be forced to the

high–impedance state by utilization of the disable feature in

the C register (bit C6). This is a patented feature. Similarly,

PDout is forced to the high–impedance state when the device

is put into standby (STBY bit C4 = high).

The PDout circuit is powered by VPD. The phase detector

gain is controllable by bits C3, C2, and C1: gain (in amps per

radian) = PDout current divided by 2π.

φR and φV (Pins 3 and 4)

Double–Ended Phase/Frequency Detector Outputs

feature. Note that when disabled or in standby, φR and φV are

forced to their rest condition (high state).

The φR and φV output signal swing is approximately from

Gnd to VPD.

Lock Detector Output (Pin 2)

This output is essentially at a high level with narrow

low–going pulses when the loop is locked (fR and fV of the

same phase and frequency). The output pulses low when fV

and fR are out of phase or different frequencies. LD is the

logical ANDing of φR and φV (see Figure 17).

This output can be enabled and disabled via the C register.

This is a patented feature. Upon power up, on–chip

initialization circuitry disables LD to a static low logic level to

prevent a false “lock” signal. If unused, LD should be disabled

and left open.

The LD output signal swing is approximately from Gnd to

VDD.

External Resistor (Pin 8)

A resistor tied between this pin and Gnd, in conjunction

with bits in the C register, determines the amount of current

that the PDout pin sinks and sources. When bits C2 and C3

are both set high, the maximum current is obtained at PDout;

see Tables 4 and 5 for other current values. The

recommended value for Rx is 3.9 kΩ (preliminary) . A value of

3.9 kΩ provides current at the PDout pin of approximately 1

mA @ VDD = 3 V and approximately 1.7 mA @ VDD = 5 V in

the 100% current mode. Note that VDD, not VPD, is a factor in

determining the current.

When the φR and φV outputs are used, the Rx pin may be

floated.

These outputs can be combined externally to generate a

loop error signal. Through use of a Motorola patented

technique, the detector’s dead zone has been eliminated.

Therefore, the phase/frequency detector is characterized by

a linear transfer function. The operation of the

phase/frequency detector is described below and is shown in

Figure 17.

POL bit (C7) in the C register = low (see Figure 14)

Frequency of fV > fR or Phase of fV Leading fR: φV =

negative pulses, φR = essentially high

Frequency of fV < fR or Phase of fV Lagging fR: φV =

essentially high, φR = negative pulses

Frequency and Phase of fV = fR: φV and φR remain

essentially high, except for a small minimum time period

when both pulse low in phase

POL bit (C7) = high

Frequency of fV > fR or Phase of fV Leading fR: φR =

negative pulses, φV = essentially high

Frequency of fV < fR or Phase of fV Lagging fR: φR =

essentially high, φV = negative pulses

Frequency and Phase of fV = fR: φV and φR remain

essentially high, except for a small minimum time period

when both pulse low in phase

These outputs can be enabled, disabled, and

interchanged via C register bits C6 or C4. This is a patented

Table 4. PDout Current*, C1 = Low with

Output A not Selected as “Port”;

Also, Default Mode When Output A

Selected as “Port”

Bit C3

Bit C2

PDout Current*

70%

80%

90%

100%

* At the time the data sheet was printed, only the 100%

current mode was guaranteed. The reduced current

modes were for experimentation only.

Table 5. PDout Current*, C1 = High with

Output A not Selected as “Port”