MC10EP89(1999) データシートの表示（PDF） - ON Semiconductor
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MC10EP89 Datasheet PDF : 8 Pages
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MC10EP89
Coaxial Cable Driver
The MC10EP89 is a differential fanout gate specifically designed to
drive coaxial cables. The device is especially useful in digital video
broadcasting applications; for this application, since the system is
polarity free, each output can be used as an independent driver. The
driver produces swings 70% larger than a standard ECL output. When
driving a coaxial cable, proper termination is required at both ends of
the line to minimize signal loss. The 1.6 (5V) and 1.4V (3.3V) swing
allow for termination at both ends of the cable, while maintaining a
800mV (5V) and 700mV (3.3V) swing at the receiving end of the
cable. Because of the larger output swings, the device cannot be
terminated into the standard VCC–2.0V. All of the DC parameters are
tested with a 50Ω to VCC–3.0V load. The driver accepts a standard
differential ECL input and can run off of the digital video broadcast
standard –5.0V supply.
• 310ps Typical Propagation Delay
• 3.0 GHz Typical Toggle Frequency
• 1.6V (5V) and 1.4V (3.3V) Swing
• PECL mode: 3.0V to 5.5V VCC with VEE = 0V
• ECL mode: 0V VCC with VEE = –3.0V to –5.5V
• Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D
• Q Output will default LOW with inputs open or at VEE
• ESD Protection: >4KV HBM, >200V MM
• New Differential Input Common Mode Range
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 152 devices
Q0 1
8 VCC
http://onsemi.com
8
1
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
HEP89
ALYW
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
PIN DESCRIPTION
PIN
FUNCTION
D, D
ECL Data Inputs
Q0, Q1, Q0, Q1
ECL Data Outputs
VCC
VEE
Positive Supply
Negative, 0 Supply
Q0 2
Q1 3
Q1 4
7D
6D
5 VEE
ORDERING INFORMATION
Device
Package
Shipping
MC10EP89D
SOIC
98 Units/Rail
MC10EP89DR2 SOIC
2500 Tape & Reel
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
© Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 1
Publication Order Number:
MC10EP89/D
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