MC10105(2000) データシートの表示（PDF） - ON Semiconductor
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MC10105 Datasheet PDF : 8 Pages
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MC10105
Triple 2-3-2-Input OR/NOR
Gate
The MC10105 is a triple 2–3–2 input OR/NOR gate.
• PD = 30 mW typ/gate (No Load)
• tpd = 2.0 ns typ
• tr, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
4
3
5
2
9
6
10
11
7
13
14
12
15
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1
1
AOUT
2
AOUT
3
AIN
4
AIN
5
BOUT
6
BOUT
7
VEE
8
16
VCC2
15
COUT
14
COUT
13
CIN
12
CIN
11
BIN
10
BIN
9
BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10105L
AWLYYWW
1
16
MC10105P
AWLYYWW
1
1
10105
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10105L
CDIP–16
25 Units / Rail
MC10105P
PDIP–16
25 Units / Rail
MC10105FN
PLCC–20
46 Units / Rail
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 6
Publication Order Number:
MC10105/D
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