MBM29DL640E データシートの表示（PDF） - Fujitsu

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MBM29DL640E

64 M (8 M X 8/4 M X 16) BIT Dual Operation

Fujitsu 

MBM29DL640E80/90/12

(Continued)

In the device, a new design concept called FlexBankTM *1 Architecture is implemented. Using this concept the

device can execute simultaneous operation between Bank 1, a bank chosen from among the four banks, and

Bank 2, a bank consisting of the three remaining banks. This means that any bank can be chosen as Bank 1.

(Refer to FUNCTIONAL DESCRIPTION for Simultaneous Operation.)

The standard device offers access times 80 ns, 90 ns and 120 ns, allowing operation of high-speed

microprocessors without the wait. To eliminate bus contention the device has separate chip enable (CE) , write

enable (WE) and output enable (OE) controls.

This device consists of pin and command set compatible with JEDEC standard E2PROMs. Commands are

written to the command register using standard microprocessor write timings. Register contents serve as input

to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the device is

similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The device is programmed by executing the program command sequence. This will invoke the Embedded

Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths and verifies

proper cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is

accomplished by executing the erase command sequence. This will invoke the Embedded Erase AlgorithmTM

which is an internal algorithm that automatically preprograms the array if it is not already programmed before

executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies

the proper cell margin.

A sector is typically erased and verified in 1.0 second (if already completely preprogrammed) .

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The device is erased when shipped from the factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low VCC detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once a program or erase cycle has been completed,

the device internally resets to the read mode.

The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program

Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read

mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the

Embedded ProgramTM *2 Algorithm or Embedded EraseTM *2 Algorithm, the device is automatically reset to the

read mode and have erroneous data stored in the address locations being programmed or erased. These

locations need rewriting after the Reset. Resetting the device enables the system’s microprocessor to read the

boot-up firmware from the Flash memory.

Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits

within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word

at a time using the EPROM programming mechanism of hot electron injection.

*1: FlexBankTM is a trademark of Fujitsu Limited.

*2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

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