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MB91310 データシートの表示(PDF) - Fujitsu

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MB91310 Datasheet PDF : 59 Pages
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MB91310 Series
• Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store in-
structions
• Register interlock functions: Facilitating coding in assemblers
• On-chip multiplier supported at the instruction level.
Signed 32-bit multiplication: 5 cycles.
Signed 16-bit multiplication: 3 cycles
• Interrupt (PC, PS save): 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instruction prefetch function implemented by a four-word queue in the CPU
• Instruction compatible with FR family
Bus interface
This bus interface is used for macro connection. (USB, MS-IF, OSDC)
• Operating frequency Max 20 MHz
• 16-bit data input/output (Interface to the USB, MS-IF, and OSDC)
• Chip-select signals can be output for completely independent eight areas allocatable in a minimum of 64 KB.
The CS1, CS2, and CS3 areas are reserved as follows. CS0, CS4, to CS3 are Mnusable.
CS1 area : USB host
CS2 area : USB function
CS3 area : MS-IF, OSDC
• Basic bus cycle : 2 cycles
• Programmable automatic wait cycle generator capable of inserting wait cycles for each area
CS1, CS2 and CS3 are reserved; their settings are fixed.
Built-in RAM
• 16 KB built RAM capacity
• This RAM can be used as instruction RAM by writing instruction code as well as data.
DMAC (DMA Controller)
• Connected to five channels (ch0, ch1 USB function; ch2 MS-IF).
• 3 forwarding factors (internal peripheral/software)
• Addressing using 32 - bit full addressing mode (increment, decrement, fixed)
• Demand transfer, burst transfer, step transfer, or block transfer
• Selectable transfer data size: 8-bit, 16-bit, or 32-bit
Bit search module (for REALOS)
• Search for the position of the bit 1/0-changed first in one word from the MSB
Reload timer (including 1 channel for REALOS)
• 16-bit PPG timer ch3
• The internal clock is optional from 2/8/32 en surroundings.
(Continued)
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