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MB91110 Series
s BLOCK DIAGRAM
FR30 CPU
(16 bit)
Bit Search Module
Instruction RAM
16 KB
I-bus
DMAC (5 ch)
DREQ0 DREQ1 DREQ2
DACK0 DACK1 DACK2
DEOP0 DEOP1 DEOP2
RAM
5 KB
D-bus (32 bit)
PLL
50 MHz
32 bit
16 bit
Bus Converter
X0 X1
RST
HST
Clock Control Unit
Instruction Cache
1 KB
Harvard
Prinston
Bus Converter
50 MHz →25 MHz
50 MHz
25 MHz
Bus Controller
C-bus
DRAM Controller
D31 ∼ D16
A23 ∼ A00
RD
WR0 ∼WR 1
RDY
CLK
CS0 ∼ CS5
BRQ BGRNT
RAS0 RAS1
CS0L CS1L
CS0H CS1H
DW0 DW1
INT0 ∼ INT7
NMI
Interrupt Control Unit
(32 bit)
Port 0 ∼ B
AN0 ∼ AN7
ATG
AVCC AVSS
AVRH AVRL
A/D Converter (8 ch)
TI0 TI1
TO0 TO1 Reload Timer (2 ch) R-bus (16 bit)
UART
SI
SO
SCK
Port E ∼ I
16 bit PPG Timer
(6 ch)
PPG0 ∼ PPG5
TRG0 ∼ TRG5
Note :
Pins are described per function. Some of the pins are multiplexed.
In the event that REALOS is used, an external interruption or built-in timer should be used to control the time.
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