MAX4850 データシートの表示（PDF） - Maxim Integrated
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MAX4850 Datasheet PDF : 16 Pages
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Dual SPDT Analog Switches with
Over-Rail Signal Handling
Test Circuits/Timing Diagrams
MAX4850_
MAX4852_
VNO
VCC
VCC
NO_
LOGIC
INPUT
IN_
GND
COM_
RL
VOUT
CL
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) VOUT = VNO
RL
RL + RON
Figure 1. Switching Time
LOGIC VCC
INPUT
0V
SWITCH VOUT
OUTPUT 0V
tR < 20ns
tF < 20ns
50%
tOFF
0.9 x V0UT 0.9 x VOUT
tON
SWITCH
INPUT
VCC + 0.5V
tHIZ
NORMAL MODE
tHIZB
HIGH-Z MODE
NORMAL MODE
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
tri
90%
50%
TxD+
A
B
INPUT A
10%
Rs
CL
tskew_i
INPUT A-
90%
50%
10%
tfi
A-
TxD-
Rs
Rs = 39Ω
CL = 50pF
B-
CL
OUTPUT B
OUTPUT B-
tro
90%
50%
10%
tskew_o
90%
50%
10%
tfo
|tro - tri| DELAY DUE TO SWITCH FOR RISING INPUT AND RISING OUTPUT SIGNALS.
|tfo - tfi| DELAY DUE TO SWITCH FOR FALLING INPUT AND FALLING OUTPUT SIGNALS.
|tskew_o| CHANGE IN SKEW THROUGH THE SWITCH FOR OUTPUT SIGNALS.
|tskew_i| CHANGE IN SKEW THROUGH THE SWITCH FOR INPUT SIGNALS.
Figure 2. Input/Output Skew Timing Diagram
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