MAX3420E データシートの表示（PDF） - Maxim Integrated
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MAX3420E Datasheet PDF : 23 Pages
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MAX3420E
USB Peripheral Controller with SPI Interface
Table 1. MAX3420E Register Map
REG
NAME
b7
b6
b5
b4
b3
b2
R0 EP0FIFO
b7
b6
b5
b4
b3
b2
R1 EP1OUTFIFO
b7
b6
b5
b4
b3
b2
R2 EP2INFIFO
b7
b6
b5
b4
b3
b2
R3 EP3INFIFO
b7
b6
b5
b4
b3
b2
R4 SUDFIFO
b7
b6
b5
b4
b3
b2
b1
b0
acc
b1
b0
RSC
b1
b0
RSC
b1
b0
RSC
b1
b0
RSC
b1
b0
RSC
R5 EP0BC
R6 EP1OUTBC
R7 EP2INBC
R8 EP3INBC
R9 EPSTALLS
R10 CLRTOGS
0
b6
b5
0
b6
b5
0
b6
b5
0
b6
b5
0
ACKSTAT STLSTAT
EP3DISAB EP2DISAB EP1DISAB
b4
b3
b2
b4
b3
b2
b4
b3
b2
b4
b3
b2
STLEP3IN STLEP2IN STLEP1OUT
CTGEP3IN CTGEP2IN CTGEP1OUT
b1
b1
b1
b1
STLEP0OUT
0
b0
b0
b0
b0
STLEP0IN
0
RSC
RSC
RSC
RSC
RSC
RSC
R11 EPIRQ
R12 EPIEN
R13 USBIRQ
R14 USBIEN
0
0
SUDAVIRQ IN3BAVIRQ IN2BAVIRQ OUT1DAVIRQ OUT0DAVIRQ
0
0
SUDAVIE IN3BAVIE IN2BAVIE OUT1DAVIE OUT0DAVIE
URESDNIRQ VBUSIRQ NOVBUSIRQ SUSPIRQ URESIRQ BUSACTIRQ RWUDNIRQ
URESDNIE VBUSIE NOVBUSIE SUSPIE URESIE BUSACTIE RWUDNIE
IN0BAVIRQ
IN0BAVIE
OSCOKIRQ
OSCOKIE
RC
RSC
RC
RSC
R15 USBCTL
HOSCSTEN VBGATE CHIPRES PWRDOWN CONNECT SIGRWU
R16 CPUCTL
0
0
0
0
0
0
R17 PINCTL
EP3INAK EP2INAK EP0INAK FDUPSPI INTLEVEL POSINT
R18 REVISION
0
0
0
0
0
1
R19 FNADDR
0
b6
b5
b4
b3
b2
R20 IOPINS
GPIN3
GPIN2
GPIN1
GPIN0 GPOUT3 GPOUT2
Note:
The acc (access) column indicates how the SPI master can access the register.
R = read, RC = read or clear, RSC = read, set, or clear.
Writing to an R register (read only) has no effect.
Writing a 1 to an RC bit (read or clear) clears the bit.
Writing a zero to an RC bit has no effect.
0
0
GPXB
0
b1
GPOUT1
0
IE
GPXA
0
b0
GPOUT0
RSC
RSC
RSC
R
R
RSC
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