A62S7332E-5 データシートの表示（PDF） - AMIC Technology

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A62S7332E-5

128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output

AMIC Technology 

A63G7332 Series

Timing Waveforms (continued)

CLK

ADSP

tKC

tKH

tKL

tADSS

tADSH

ADSC

ADDRESS A1

GW,BWE,

BW1-BW4

(NOTE *3)

CE

(NOTE *2)

tAS tAH

A2

tCES

tCEH

ADV

A3

A4

tWS

tWH

A5

A6

OE

DIN

DOUT

High-Z

tKQ

tKQLZ

tOEHZ

High-Z

Q(A1)

Back-to-Back READs

Q(A2)

tDS

tDH

D(A3)

Single WRITE

tOELZ

tKQ

Q(A3)

Pass-through

READ

(NOTE *4)

(NOTE *1)

Q(A4)

Q(A4+1)

Q(A4+2)

BURST READ

Q(A4+3)

D(A5)

D(A6)

Back-to-Back

WRITEs

Read/Write Timing

Notes:

*1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the internal burst address immediately

following A4.

*2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is

LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.

*3. Byte Write enables are decided by means of a Write truth table.

*4. Pass-through occurs when data is first written, then Read in sequence.

PRELIMINARY (December, 1998, Version 2.1)

13

AMIC Technology, Inc.

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