M80C287 データシートの表示（PDF） - Intel

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M80C287

80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION

Intel 

M80C287

Figure 4 shows the six exception flags in bits 5– 0 of

the status word Bits 5– 0 are set to indicate that the

M80C287 has detected an exception while execut-

ing an instruction A later section entitled ‘‘Exception

Handling’’ explains how they are set and used

Note that when a new value is loaded into the status

word by the FLDENV or FRSTOR instruction the

value of ES (bit 7) and its reflection in the B-bit (bit

15) are not derived from the values loaded from

memory but rather are dependent upon the values of

the exception flags (bits 5 – 0) in the status word and

their corresponding masks in the control word If ES

is set in such a case the ERROR output of the

M80C287 is activated immediately

ES is set if any unmasked exception bit is set cleared otherwise

See Table 2 2 for interpretation of condition code

TOP Values

000 e Register 0 is Top of Stack

001 e Register 1 is Top of Stack







111 e Register 7 is Top of Stack

For definitions of exceptions refer to the section entitled ‘‘Exception Handling ’’

Figure 4 Status Word

271092 – 3

5

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