M5M4V64S20ATP-10L データシートの表示（PDF） - MITSUBISHI ELECTRIC

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M5M4V64S20ATP-10L

64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

MITSUBISHI ELECTRIC  

SDRAM (Rev.1.3)

Mar98

MITSUBISHI LSIs

M5M4V64S20ATP-8A,-8L,-8, -10L, -10

64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

PIN FUNCTION

CLK

CKE

/CS

/RAS, /CAS, /WE

Input

Input

Input

Input

Master Clock: All other inputs are referenced to the rising edge of CLK.

Clock Enable: CKE controls internal clock. When CKE is low, internal clock

for the following cycle is ceased. CKE is also used to select auto / self

refresh. After self refresh mode is started, CKE becomes asynchronous

input. Self refresh is maintained as long as CKE is low.

Chip Select: When /CS is high, any command means No Operation.

Combination of /RAS, /CAS, /WE defines basic commands.

A0-11

BA0,1

DQ0-3

DQM

Vdd, Vss

VddQ, VssQ

Input

A0-11 specify the Row / Column Address in conjunction with BA0,1. The

Row Address is specified by A0-11. The Column Address is specified by

A0-9 . A10 is also used to indicate precharge option. When

A10 is high at a read / write command, an auto precharge is performed.

When A10 is high at a precharge command, all banks are precharged.

Input

Bank Address: BA0,1 specifies one of four banks to which a command is

applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.

Input / Output

Input

Data In and Data out are referenced to the rising edge of CLK.

Din Mask / Output Disable: When DQM is high in burst write, Din for the

current cycle is masked. When DQM is high in burst read,

Dout is disabled at the next but one cycle.

Power Supply Power Supply for the memory array and peripheral circuitry.

Power Supply VddQ and VssQ are supplied to the Output Buffers only.

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