M5M4V64S20ATP-10L データシートの表示（PDF） - MITSUBISHI ELECTRIC
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M5M4V64S20ATP-10L Datasheet PDF : 51 Pages
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SDRAM (Rev.1.3)
Mar98
MITSUBISHI LSIs
M5M4V64S20ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM
from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by
CLK
setting the mode register (MRS). The mode register stores these data
until the next MRS command, which may be issued when both banks
/CS
are inÅ@idle state. After tRSC from a MRS command, the SDRAM is
/RAS
ready for new command.
/CAS
/WE
BA0,1 A11-A0
V
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 WM 0 0 LTMODE BT
BL
LATENCY
MODE
CL
000
001
010
011
100
101
110
111
/CAS LATENCY
R
R
2
3
R
R
R
R
BURST
LENGTH
BL
000
001
010
011
100
101
110
111
BT= 0
1
2
4
8
R
R
R
FP
BT= 1
1
2
4
8
R
R
R
R
WRITE
MODE
0 BURST
1 SINGLE BIT
BURST
TYPE
0 SEQUENTIAL
1
INTERLEAVED
R: Reserved for Future Use
FP: Full Page
MITSUBISHI ELECTRIC
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